View CY621472E30LL-45ZSXIT_8572071.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy621472e30 mobl ? 4-mbit (256 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-67798 rev. *e revised april 3, 2014 4-mbit (256 k 16) static ram features very high speed: 45 ns temperature range ? industrial: ?40 c to +85 c wide voltage range: 2.20 v to 3.60 v ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a (industrial) ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 44-pin thin small outline package (tsop) ii package byte power down feature functional description the cy621472e30 is a high per formance cmos static ram (sram) organized as 256k words by 16 bits. this device features advanced circuit desi gn to provide ultra low active current. it is ideal for provid ing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99 percent when deselected (ce 1 high or ce 2 low or both ble and bhe are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce 1 high or ce 2 low) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) write operation is active (ce 1 low and ce 2 high and we low) to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location spec ified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce 1 low and ce 2 high and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. 256k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce 1 we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 bhe ble ce power down circuit logic block diagram ce 2
cy621472e30 mobl ? document number: 001-67798 rev. *e page 2 of 16 contents product portfolio .............................................................. 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy621472e30 mobl ? document number: 001-67798 rev. *e page 3 of 16 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy621472e30ll industrial 2.2 3.0 3.6 45 2 2.5 15 20 1 7 pin configuration figure 1. 44-pin tsop ii pinout 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce 1 we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss ce 2 10 a 17 note 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 4 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential ...........................?0.3 v to +3.9 v (v ccmax + 0.3 v) dc voltage applied to outputs in high z state [2, 3] ............ ?0.3 v to 3.9 v (v ccmax + 0.3 v) dc input voltage [2, 3] ......... ?0.3 v to 3.9 v (v ccmax + 0.3 v) output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................ > 2001 v latch up current...................................................... > 200 ma operating range device range ambient temperature v cc [4] cy621472e30ll industrial ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [5] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 v i ol = 2.1 ma, v cc = 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?1520ma f = 1 mhz ? 2 2.5 i sb1 [6] automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2 v, ce 2 ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60 v ?17 ? a i sb2 [6] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?17 ? a notes 2. v il(min) = ?2.0 v for pulse durations less than 20 ns. 3. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 4. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc(min) and 200 ? s wait time after v cc stabilization. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 6. chip enables (ce 1 and ce 2 ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 5 of 16 capacitance parameter [7] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [7] description test conditions 44-pin tsop ii package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 ? c/w ? jc thermal resistance (junction to case) 13 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v note 7. tested initially and after any design or process changes that may affect these parameters.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [8] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [9] data retention current v cc = 1.5 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?0.87 ? a t cdr [10] chip deselect to data retention time 0??ns t r [11] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform [12, 13] v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce or bhe .ble notes 8. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 9. chip enables (ce 1 and ce 2 ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 10. tested initially and after any design or process changes that may affect these parameters. 11. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 12. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 13. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble .
cy621472e30 mobl ? document number: 001-67798 rev. *e page 7 of 16 switching characteristics over the operating range parameter [14] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low/ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [15] 5 ? ns t hzoe oe high to high z [15, 16] ? 18 ns t lzce ce 1 low/ce 2 high to low z [15] 10 ? ns t hzce ce 1 high/ce 2 low to high z [15, 16] ? 18 ns t pu ce 1 low/ce 2 high to power-up 0 ? ns t pd ce 1 high/ce 2 low to power-down ? 45 ns t dbe ble /bhe low to data valid ? 45 ns t lzbe ble /bhe low to low z [15, 17] 5 ? ns t hzbe ble /bhe high to high z [15, 16] ? 18 ns write cycle [18, 19] t wc write cycle time 45 ? ns t sce ce 1 low/ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [15, 16] ? 18 ns t lzwe we high to low z [15] 10 ? ns notes 14. test conditions for all parameters other than tri-state parameter s assume signal transition time of 3 ns (1 v/ns) or less, t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 17. if both byte enables are together, this value is 10 ns. 18. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble , or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. 19. the minimum write cycle pulse width for write cycle 4 (we controlled, oe low) should be equal to the sum of t hzwe and t sd .
cy621472e30 mobl ? document number: 001-67798 rev. *e page 8 of 16 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [20, 21] figure 5. read cycle no. 2 (oe controlled) [21, 22, 23] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 20. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 21. we is high for read cycle. 22. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 23. address valid before or similar to ce and bhe , ble transition low.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 9 of 16 figure 6. write cycle no. 1 (we controlled) [24, 25, 26, 27] figure 7. write cycle no. 2 (ce controlled) [24, 25, 26, 27] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 28 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 28 notes 24. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 25. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble , or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by goi ng inactive. the data input setup and hold timing must be referenced to the edge o f the signal that terminates the write. 26. data i/o is high impedance if oe = v ih . 27. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period, the i/os are in output state. do not apply input signals.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 10 of 16 figure 8. write cycle no. 3 (we controlled, oe low) [29, 30, 31] figure 9. write cycle no. 4 (bhe /ble controlled, oe low) [29, 30] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 32 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 32 data i/o address ce we bhe /ble notes 29. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 30. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 31. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd. 32. during this period, the i/os are in output state. do not apply input signals.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 11 of 16 truth table ce 1 ce 2 we oe bhe ble i/os mode power hx [33] x x x x high z deselect/power-down standby (i sb ) x [33] l x x x x high z deselect/power-down standby (i sb ) x [33] x [33] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h h l l high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) lhlxlhdata in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 33. the ?x? (don?t care) state for the chip enables (ce 1 and ce 2 ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
cy621472e30 mobl ? document number: 001-67798 rev. *e page 12 of 16 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 cy621472e30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) industrial temperature range: i = industrial pb-free package type: zs = 44-pin tsop ii speed grade: 45 = 45 ns low power voltage range: 30 = 3 v typical process technology: e = 90 nm dual chip enable bus width: 7 = 16 density: 4 = 4-mbit family code: 621 = mobl sram family company id: cy = cypress cy 45 zs 621 4 7 e 30 ll x 2 - i
cy621472e30 mobl ? document number: 001-67798 rev. *e page 13 of 16 package diagram figure 10. 44-pin tsop ii package outline, 51-85087 51-85087 *e
cy621472e30 mobl ? document number: 001-67798 rev. *e page 14 of 16 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy621472e30 mobl ? document number: 001-67798 rev. *e page 15 of 16 document history page document title: cy621472e30 mobl ? , 4-mbit (256 k 16) static ram document number: 001-67798 rev. ecn no. orig. of change submission date description of change ** 3184883 rame 03/01/2011 new data sheet. *a 3223503 rame 04/15/2011 overline bar ce 2 removed from the truth table. updated all notes as per template. *b 3261142 rame 05/19/2011 updated switching characteristics (corrected the min value of t lzbe parameter). added ordering information and ordering code definitions . added acronyms and units of measure . *c 3365953 aju 09/08/2011 changed datasheet status from preliminary to final. updated 44-pin tsop ii package spec. *d 3414567 tava 10/20/2011 replaced cy62147ev30 wit h cy621472e30 through out the data sheet. *e 4331825 nile 04/03/2014 updated switching characteristics : added note 19 and referred the same note in ?write cycle?. updated switching waveforms : added note 31 and referred the same note in figure 8 . updated package diagram : spec 51-85087 ? changed revision from *d to *e. updated in new template. completing sunset review.
document number: 001-67798 rev. *e revised april 3, 2014 page 16 of 16 mobl is a registered trademark, and more battery life is a trademark of cypress semiconductor. all product and company names me ntioned in this document are the tr ademarks of their respective holders. cy621472e30 mobl ? ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

▲Up To Search▲

Price & Availability of CY621472E30LL-45ZSXIT

	To Download CY621472E30LL-45ZSXIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .